Duco van Amstel - Data Locality on Manycore Architectures

12:00
Monday
18
Jul
2016
  • Thesis defence
Organized by: 
Duco van Amstel
Speaker: 
Duco van Amstel
Teams: 

 

Venue :

Presentation room at the main entrance of the CEA Grenoble;

 
(In order to reach the presentation room take the B tram to the CEA-Cambridge stop and then walk to the main entrance reception building)
 
Thesis committee :
 
- Dr. François IRIGOIN - Director of the Centre de Recherche en Informatique at Mines ParisTech (Reviewer)
- Dr. Albert COHEN - Research Director and leader of the PARKAS team at Inria (Reviewer)
- Dr. P. SADAYAPPAN - Professor at the Ohio State University, Columbus (Examiner)
- Dr. François BODIN - Professor at Université de Rennes 1 and Research Director in the Alf team at Inria (Examiner)
- Dr. Fabrice RASTELLO - Research Director and leader of the CORSE team at Inria (Advisor)
- Dr. Benoît DE DINECHIN - CTO of Kalray (Co-advisor)
 

The growing number of cores on modern-day processors and the evolution of their overall architecture continues to bring new challenges to code optimizations for these platforms. Running code on such architectures requires data transfers between the multiple memories located throughout the chip that are expensive in both time and energy. In order to limit the impact of these transfers on the performances of applications we present a new approach that combines both a model for memory-usage and a code transformation. This transformation consists of the rescheduling of code at various levels with the goal of regrouping the different accesses to the same data element in a small window of time. The implementation of this new method is illustrated with multiple use-cases for which the effects on data transfers are evaluated..